A primary trend in electronics industry is product miniaturization. Product miniaturization involves ways to make products lighter, smaller, and less expensive yet more powerful, reliable, user-friendly, and functional. Some examples of products which have been miniaturized includes cellular phones, personal and sub-notebook computers, pagers, Personal Computer Memory Card International Association (PCMCIA) cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components.
One of the factors that may limit product miniaturization involve packaging of the product. With integration of increased functionality in silicon chips as per Moore's Law, it is also desirable to shrink the package. One way to shrink the package involves a 2-dimensional (2D) level packaging. Some examples of 2D level packaging involves chips first or embedded chip packaging and embedded wafer level packaging.
Chips first or embedded chip packaging is a way to overcome these recent packaging integration challenges. One example of chips first or embedded chip packaging involves replacement of the lead frame based peripheral array packages with the plastic ball grid array (PBGA), in which the die is electrically connected to printed circuit board (PCB) substrate by wire bonding or flip chip technology. The chip is further covered with molding compound to avoid chip damage.
Another example of chips first or embedded chip packaging involves a method of embedding singulated die based on PCB technology. The singulated die is first attached onto the copper (Cu) base plate in the cavity of a PCB substrate and subsequent Cu rewiring and vias are then built-up on top of the active side based on the PCB technology. Finally, solder balls are formed on top of the Cu pads for electrical interconnection.
Embedded wafer level packaging takes chips first or embedded chip packaging to the next step, eliminating the PCB substrate, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection. By removing the PCB substrate, packaging cost is reduced and its electrical performance is improved.
An example of embedded wafer level packaging involves a fabrication method based on wafer level processing. The fabrication method involves attaching singulated dies with active top side down onto a thermo-sensitive adhesive material coupled to a carrier plate. A wafer molding process is then used to encapsulate the attached dies on the carrier plate. The carrier plate is then separated and the dies are now housed onto mold compound forming a reconstituted wafer. Redistribution layer can be formed on the reconstituted wafer using conventional lithographic process. Solder bumps can also be formed on the wafer level prior to singulation.
However, one of the major challenges in embedded wafer level packaging is the warpage of the wafers. Therefore, there is a need for an improved solution to fabricate an embedded wafer level package semiconductor structure with low warpage.